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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
  • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
  • H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
  • H10D84/401—Combinations of FETs or IGBTs with BJTs
  • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
  • H10D84/406—Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

• ABSTRACT A floating gate transistor comprising a floating silicon or metal gate in a field effect transistor which is particularly useful in a read-only memory is disclosed.
• the gate which is surrounded by an insulative material such as SiO is charged by transferring charged particles (i.e., electrons) across the insulation from the substrate during an avalanche (breakdown) condition in the source or drain junctions of the transistor.
• FIG. 1 illustrates a typical prior art embodiment of a floating gate transistor; its impracticalities will be discussed in conjunction with that figure.
• a transistor which in its presently-preferred embodiment comprises a floating gate insulator semiconductor device is described.
• the transistor comprises a substrate of a first conductivity type and a pair of spaced apart regions of the opposite conductivity type to the first conductivity type disposed in the substrate.
• a gate is spatially disposed between the regions and separated therefrom by an insulative layer.
• the gate is substantially surrounded by an insulative layer that may be of the same type that separates it from the region or a different type and no electrical connections are made to the gate.
• Contact means such as metal contacts are provided to the regions.
• the substrate comprises an N-type silicon and the regions are of a P-type conductivity.
• the gate may be conductive or semiconductor materials such as silicon or germanium, aluminum, molybdenum or other conductive metals.
• An electrical charge is placed on the gate by applying a voltage between one of the regions and the substrate of sufficient magnitude to cause a breakdown (e.g., an avalanche injection condition) in at least one of the junctions defined by the interface of the regions and substrate. This causes electrons to enter and pass through the insulation separating the substrate and gate and to charge the gate.
• the charge may be removed from the gate by subjecting the transistor to X-rays or to ultraviolet light.
• Another object of the present invention is to provide a storage retention transistor which has the capability of providing long term storage without the continuous application of power.
• FIG. 1 illustrates a cross-section of a floating gate transistor as disclosed in the prior art.
• FIG. 2 illustrates a cross-section of a floating gate transistor as described by the present invention.
• a field effect transistor having a floating gate which is particularly useful as a component in a read-only memory is disclosed.
• the presence or lack of an electrical charge on the gate is sensed and this infonnation used in the same manner as other bi-stable memory devices such as magnetic cores and flip-flops are used in forming a memory array.
• the charge remains pennanently 10 years at C.) on the gate and the existence or non-existence of the charge on the gate is readily ascertainable by sensing the conductivity characteristics between the source "and drain region of the field effect transistor.
• the conductivity characteristics between the source "and drain region of the field effect transistor typically, the
• field effect transistor readily conducts a current between its source and drain once the gate is negatively charged and likewise the transistor will not conduct a current when the gate is not charged assuming that the voltage applied to the source or drain junction is less than that required to cause an avalanche breakdown in the transistor.
• the transistor comprises a field ef fect device having a source and drain hereafter interchangeably referred to as regions 13 and 15 which are produced in a substrate 10.
• the substrate 10 is opposite in conductivity type to the regions 13 and 15.
• the regions 13 and 15 would be a P-conductivity type.
• Metal contacts 11 are coupled to the regions 13 and 15 to allow a current to be passed between the regions 13 and 15.
• An insulative layer 12 separates the floating gate 14 from the substrate 10 and regions 13 and 15.
• a second insulative layer 16 which serves to completely surround the floating gate 14, separates the charging gate 18 from the remainder of the transistor device.
• the gates 14 and 18 are made of material such as aluminum, the regions 13 and 15 and substrate 10 may be made from such material as appropriately doped silicon or germanium.
• a charge if one is desired, is placed on the floating gate 14, by applying a voltage between the charging gate 18 via lead 19 and substrate 10.
• a charge is transported from the substrate across the insulation 12 into the floating gate 14.
• layer 12 be relatively thin and that a high ratio of dielectric constants exist between the materials used for layers .16 and 12. This produces a higher field strength across layer 12 than layer 16 and allows a charge to betransported onto the gate 14.
• it is very difficult to deposit a metal layer over this thin insulation without producing current paths between the metal and substrate. Also, to
• FIG. 2 a cross-sectional view of a field effect transistor built in accordance with the teachings of the present invention is illustrated. While the present invention is illustrated in conjunction with a particular field effect device, it is readily apparent that other types of field effect transistors may be modified in accordance with the teachings of this patent and utilized as a component in a read-only array as well as in other applications.
• the transistor of FIG. 2 comprises a pair of spaced apart regions 22 and 24 (source and drain) which are opposite in conductivity type to the substrate 20.
• the regions which define a pair of PN junctions, one between each region and the substrate may be produced on the substrate 20 utilizing commonly known techniques.
• the gate 28 of the transistor which is spatially disposed between the regions 22 and 24 preferably completely enclosed within insulative layers 26 and 30, so that no electrical path exists between the gate 28 and any other parts of the transistor.
• Metal contacts 32 and 33 are utilized to provide contacts to the regions 22 and 24, respectively.
• the transistor of FIG. 2 may be produced using known MOS or silicon gate technology.
• the substrate comprises an N-type silicon
• the regions 22 and 24 comprise P type regions
• the contacts 32 and 33 are aluminum
• the insulative layer 26 and layer 30 may comprise a silicon oxide (e.g., SiO, SiO
• SiO silicon oxide
• the insulative layer 12 of the transistor illustrated in FIG. 1 had to be relatively thin in order to charge the gate 14.
• the insulative layer 26 which separates the gate 28 from the substrate 20 may be relatively thick; for example, it may be 500 A. to 1,000 A. This thickness may be readily achieved utilizing present MOS technology.
• the layer 30 in the presently preferred embodiment comprises approximately 1,000 A. of the thermally grown silicon oxide directly above the gate 28 and approximately 1 .0 of vapor deposited silicon oxide above the thermal oxide. I I I
• the gate 28 of the transistor of FIG. 2 may be charged in accordance with the teachings of the present invention without the use of a charging gate, such as gate 18 of FIG. 1.
• the charge is placed on the gate 28 through the metal contacts 32, 33 and the substrate.
• the charge is transferred to the gate 28 through the insulative layer 26 by causing an avalanche breakdown condition in either of the PN junctions defined by regions 22 and 24 in the substrate20.
• region 22 is illustrated coupled to the ground via the contact 32 and lead 35 and region 24 is illustrated coupled to a negative voltage via contact 33 and lead 34; also, the substrate is grounded.
• a voltage is applied to lead 34 of sufficient magnitude to cause an avalanche breakdown of the junction defined by region 24 and substrate 20.
• the gate 28 When the avalanche breakdown occurs, the high energy electrons generated in this PN junction depletion region pass through the insulative layer 26 onto the gate 28 under the influence of the fringing field 36. Once the gate 28 is charged, it will remain charged for usefully long periods since no discharge path is available for the accumulated electrons within gate 28. (Note that the entire. gate 28 is surrounded by an insulative layer such as a thermal oxide.) After the voltage has been removed from the transistor, the only other electric field in the structure is due to the accumulated electron charge within the gate 28 and this is not sufi'icient to cause charge to be transported across the insulative layer 26. (Note that the gate 28 could have been charged in the same manner as described with the substrate and/or contact 32 biased at some potential other than the ground potential.)
• a charge on a gate such as gate 28 should remain there for periods greater than years even at operating temperatures of 125 C.
• the avalanche junction breakdown described occurs at a voltage of approximately 30 volts utilizing typical MOS devices and assuming an oxide thickness for layer 26 of approximately l,000 A.
• the existence or non-existence of a charge on gate 28 may be determined by examining the characteristics of the transistors at the contacts 32 and 33. This may be done by applying a voltage between contacts 32 and 33. This voltage should be less than that required to cause an avalanche breakdown. The transistor more readily conducts if a charge exists on gate 28 when compared to the conducting of the same transistor without a charge on its gate.
• a number of methods have been found for removing the charge from a gate 28. If the transistor of FIG. 2 is subjected to X-ray radiation, the charge on gate 28 is removed. Experiments have shown that radiation of 2X10 rads when applied even through the package containing the transistor will cause the charge to be removed from gate28. Also, ultra-violet light of the order of magnitude 4evs when applied directly to the transistor (not through the transistor package) will cause the charge to be removed from the gate 28. Subjecting the transistor to high temperatures (i.e., 450 C.) will also cause the charge to be removed, but this technique may result in permanently damaging .the device.
• a field effect transistor containing a floating gate which is completely surrounded by insulative material such as silicon dioxide, particularly adaptable for use in a read-only memory has been described.
• the transistor may be manufactured utilizing known MOS techniques.
• the contacts to the transistor which are used to determine the existence or nonexistence of a charge on the gate are also used to place a charge on the gate.
• a charging gate is not required and relatively thick easy to develop thermal oxide layers may be used between the floating gate and the substrate.
• a storage device comprising:
• a floating gate disposed spatially between said pair of spaced apart regions; an insulative layer between said body and said floating gate; insulative means covering said floating gate, said insulative means being free of any metallization employed primarily for charging said floating gate;
• the storage device defined in claim 6 including contact means for providing contact to said pair of spaced apart regions.
• a storage device comprising: a semiconductor substrate of a first conductivity type; a pair of spaced apart regions of opposite conductivity type, forming a pair of PN junctions in said substrate; a floating gate disposed spatially between said spaced apart regions; and insulative layer disposed between said substrate and said floating gate; and insulative means covering said floating gate, said insulative means being free from any metallization employed primarily for charging said floating gate;
• a method for placing an electrical charge on said gate comprising applying a voltage to at least one of said regions and said substrate of sufficient magnitude to cause an avalanche injection thereby causing electrons to pass through the insulation from said substrate to said floating gate to charge said gate.

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Cited By (60)

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Citations (3)

• 1970
  • 2025-08-06 US US46148A patent/US3660819A/en not_active Expired - Lifetime
• 1977
  • 2025-08-06 JP JP10177977A patent/JPS5333589A/en active Granted

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